A newly-designed integrated circuit (“IC”) is typically fabricated over a process, involving preparation of silicon substrate wafers, generation of masks, doping of the silicon substrate, deposition of metal layers, and so on. The IC typically has many physical layers on this substrate with various individual electronic components, such as resistors, capacitors, diodes, and transistors, collectively forming one or more electrical circuits. The metal layers, which may be aluminum, copper, or other conductive material, provide the interconnection mesh between the various individual electronic components to form integrated electrical circuits. Vias formed of electrically conductive material provide communication pathways between various metal layers. Contacts provide communication links between metal layers and individual electronic components embedded in the silicon substrate. The metal layers as expected must be placed very precisely and their thicknesses must be controlled. Various monitoring tools are employed to make the CD (“critical dimension”) measurements during the fabrication of the IC. The goal being a flawless (within acceptable tolerances for that process) execution of the fabrication process.
Unfortunately, a new complex IC rarely works as expected when first fabricated. Normally, some defects in the operation of the IC are discovered during testing. Also, some functions of the IC may only operate properly under limited conditions, but fail when operated across a full range of temperatures, frequencies and voltages in which the IC is expected to perform. Once the IC has been tested, the designer may need to change the design, initiate the manufacture of a second prototype IC via the lengthy process described above, and then test this new IC. However, no guarantee exists that the design changes will correct the problems previously encountered, or that all of the problems in the previous version of the IC have been discovered. Sometimes a failure is due to the design, the process, and the interaction of the process with the specifics of the design layout. Often times a cross section of the devices vertical and horizontal structure is required during fabrication or after to learn what the problem is and why.
Charged particle beam systems, such as focused ion beam (“FIB”) systems and electron beam (“e-beam”) systems, laser based systems, and other integrated circuit operation platforms have found many applications in various areas of science and industry. Particularly in the semiconductor industry, charged particle beam systems are used for integrated circuit edits, probe point creation, failure analysis, and numerous other applications including cross section analysis. More generally, servicing platforms may be used for testing, analyzing, editing, and/or repairing an IC. For example, charged particle beam systems may be used to edit a circuit (“circuit editing”) in order to validate design changes and thereby avoid some or all of the expense of validating design changes through fabrication. Particularly, a FIB instrument typically includes a particle beam production column designed to precisely focus an ion beam on the IC at the place intended for the desired intervention. Such a column typically comprises a source of ions, such as Ga+ (Gallium), produced from liquid metal. The Ga+ is used to form the ion beam, which is focused on the IC by a focusing device comprising a certain number of electrodes operating at determined potentials so as to form an electrostatic lens system. Other types of charged particle beam systems deploy other arrangements to produce charged particle beams capable of various types of circuit edits and operations generally. Further, laser-based systems deploy various types of lasers for purposes of laser based circuit editing. FIB systems also may include co-axial photon-ion columns as described with respect to U.S. Patent Application US 20030102436 titled “Column Simultaneously Focusing a Particle Beam and an Optical Beam,” which is hereby incorporated by reference herein.
As mentioned above, IC manufacturers sometimes employ a FIB system to make CD measurements or conduct a failure analysis on a prototype IC. CD measurements and failure analysis in these cases provide detailed information about the physical characteristics of structures at sub-process dimensions, some times near the atomic level. Typically, the CD measurements and failure analysis is performed using a FIB instrument in conjunction with Scanning Electron Microscope (“SEM”) imaging. The FIB removes device material to form a trench (cross section trench) at a specific area of interest predetermined by statistical requirements of CD measurements or by electrical failure localization techniques. The orientation of the face of the trench would be predetermined also. SEM imaging requires this milled trench and polishing of only one side of a target cross section. The differences between a CD measurement tool and a FIB based physical failure analysis tool are the samples being analyzed. Generally, the CD measurement tool is used to examine structures on wafers whereas the failure analysis tool is used to examine discrete die. However, the CD tool can examine discrete die when properly mounted and the failure analysis tool can examine wafer pieces which are small enough to be mounted.
SEM imaging provides structural information on a selected area, which is used to identify potential failures in the prototype IC. The spatial resolution of the SEM, however, is limited by the size of the electron spot, which is dependent on the magnetic electron-optical system, which produces the scanning beam as well as on the energy of the electron probe. The resolution is also limited by the size of the interaction volume, or the extent of material, which interacts with the electron beam. This process requires extensive milling and layer thinning to get adequate image resolutions and may become impractical for structures smaller than the 45 nm process.
For imaging when SEM is insufficient to yield a desired resolution, a device processed with a FIB is imaged with a Scanning Transmission Electron Microscope (STEM) or a Transmission Electron Microscope (TEM). TEM imaging of a sample prepared with an FIB instrument as well as a comparison to SEM imaging is discussed in “Copper/low-K Process Characterization for 90NM Technology Using SEM and TEM Imaging,” Zimmerman et al., Proceedings of 12th IPFA 2005, Singapore (2005), which is hereby incorporated by reference herein. STEMs and TEMs involve imaging techniques whereby a beam of electrons are focused onto a specimen causing an enlarged version to appear on an energy sensitive imaging detector such as a fluorescent screen or layer of photographic film or digital camera. Preparation of a sample for STEM or TEM imaging requires extensive milling and cross sectional thinning to get adequate image resolution, which is time consuming.
Particularly for TEM or STEM imaging, the sample being scanned must be very thin, on the order of 100 nm. As such, to image a cross section of an IC, a cross section trench must be milled and polished on either side of the target section. The milling and polishing of such a thin sample region often results in partial or complete destruction of the sample region. SEM imaging requires a trench and polishing of only one side of a target cross section; thus, preparation of a sample for TEM or STEM imaging has the greater potential for failure compared with preparation for SEM imaging.
Therefore, there is a growing need in the art for CD measurement and failure analysis methods that are practical in providing information more rapidly and yet produces adequate images and data from IC structures of interest.